Backplane design for optical network

We had cooperated with a European IC design team to design a reference board for their 3.125Gbps network processor. The original backplane had negative voltage margin and was not able to meet the design spec for jitter due to impedance mismatching and incorrect package model. After engaging with the client, we quickly developed action plan to address these issues. The package model is extracted using full-wave Electromagnetic solver. Other system parts were also modeled properly for the whole channel simulation (see Figure 1 for system block diagram). Solution space was obtained through sweeping design variables and analyzing results with DOE method to improve simulation efficiency. With the results we delivered, the customer’s prototype board passed system test. Figure 2 and 3 present the eye diagram probed at the receiver side in the original and optimized design respectively.

Figure 1. System Block Diagram

      Figure 2. Eye Diagram at receiver side in original design               Figure 3. Eye Diagram at receiver side in optimized design

IBIS Modeling for IO buffers

With signals traveling faster, accurate modeling and simulation of the IO buffers is in the critical path towards the success of the design. IBIS (I/O Buffer Information Specification) became the right choice of IC manufacturers as it gives their clients access to IO buffer models while protecting their intellectual property. However, the challenge is for the IBIS model to authentically replicate the behavior of the transistor circuits in various applications.

One of our American clients needs to provide the full-chip IBIS model to their customers. By simply fitting one VT curve, they created the IBIS model. But they could not be satisfied with the performance of the model. Figure 4. shows a correlation between output waveform generated by an IBIS through merely VT curve fitted method to waveform generated by transistor circuit simulation. After engaging with the client, our IBIS support team regenerated the IBIS model using algorithm with independent intellectual property rights and achieved excellent results. Figure 5. presents the correlations between output waveform from our IBIS model to waveform from transistor circuit model.

Figure 4. Correlation between output waveform from original IBIS model (yellow) to transistor model (red)

Figure 5. Correlation between output waveform from regenerated IBIS model (yellow) to transistor model (red)

High-Speed Package Design and Modeling

Digital communications and wireless applications have created compelling demand for high-speed package design and modeling. Making the right choice of package and its accurate model can be crucial to the performance of the system. Figure 6. illustrates the 3-dimentional model our package design team built for an Israeli client’s WLAN transceiver chip. Scattering parameters of the package was extracted from model using full-wave electromagnetic solver and correlated well with the S parameters measured by Vector Network Analyzer (See Figure 7 for detail). This chip has been widely used in the next generation mobile computing devices.

Figure 6. Package model for WLAN transceiver chip

Figure 7. Correlation of S parameters by simulation and measurement

Notes for Figure 7: Signal number 1,2,3,4,5 are simulation results of five different pin of the package. Signal number 6 is result measured by VNA on one of the pin number 1. Both Linear plot (left) and Smith Chart (right) demonstrate good match.