Focus On Your Signal 　 　 　 　 　

Produce & Service


High Speed System Design

　
　

     

Different from traditional system design, high speed system design requires special care to floor-plan and board layout. A system designed merely with routability considerations while not from holistic system perspective is likely to bring troubles in later design stages and cause schedule delay or even design failure.

Our high speed system design consulting services aim to helping clients with system floor-plan and design guide. We provide:

  • Comprehensive system analysis

  • System floor-plan

  • Various interface specifications

  • Risk assessment on high speed or complex interfaces

  • Design verification

  • Design guideline

　

High Speed Backplane Design

　

 

The signals traveling through backplanes and line cards have speeded up to Giga Hertz from several hundred Mega Herz. To catch up with its speed, bus architecture has evolved from parallel to serial. While consumers enjoy the broadband internet surfing and smaller access devices, electronic designers are challenged with high performance requirements and tight margin for PCBs and packages. To ensure short Time To Market, they often have to control impedance of PCB traces, take serious consideration in  Vias placement, minimize cross-talk between signals, or run complete system simulation.

　

We have provided consultation to industry-leading companies on backplane designs based on various interface specifications, such as PCI-Express, XAUI, etc. We provide:

  • Complete solution to backplane, high-speed interconnect design

  • Consultation on backplane, high-speed interconnect design

  • Debugging services in backplane, high-speed interconnect design



 Signal Integrity Analysis

　

      

For high speed system, signal integrity has come to be an outstanding issue. Signal integrity analysis for high speed IO interfaces is critical for the products to function as they are designed to. We provide:

　

  • High-speed channel analysis: chip to chip signaling analysis

  • Accurate frequency domain model for components

  • Worst case analysis taking into account manufacture tolerance

  • System simulation with both transistor buffers and IBIS model

  • Recommendation of system topology

  • Recommendation of package type, connectors

  • Layout design guideline

  • Recommendation of equalization strategy for IO designs

　


 Power Integrity Analysis

　

With transistors switching faster, electronic devices become sensitive to power supply noise. It is not rare for incompetent power design to cause system failure. One of the trouble-makers is Simultaneous Switching Noise (SSN), which increases jitter, degrades other timing indicators and  triggers logic errors in worse cases. For the device to meet design target, SSN needs to be restrained within allowable amount by choosing the right stack-up, implementing proper power/ground plane layout and decoupling techniques.

Our experience in power delivery network design, modeling, analysis and optimization extends to IC, package, and PCB designs in various applications – computing, communications, automobile, medical care, aviation, etc. We provide:

  • PCB stack-up design

  • Power/ground plane layout scheme

  • Power distribution scheme

  • Power delivery network model extraction

  • Simultaneous switching noise analysis and solution

  • Design optimization for power supply to clock, PLL, oscillator circuits

  • Design optimization for power supply to reduce EMI

  • Silicon buffer optimization for power performance

  • Signal quality analysis with power supply noise

  • Decoupling scheme and via placement

　

　
　

EMI/EMC Analysis

　

Across various fields such as telecommunication, computing, marine navigation, medical industry, no modern electronic system is immune from electromagnetic interference. Design for EMI from the beginning can save cost, time for your products. We provide:

  • Pre-layout design guide

  • Post-layout EMI/EMC evaluation

  • Fast diagnosis of EMI/EMC problem


　

 Passive Component Modeling

　

　		 　

Accurate modeling for passive components including discrete components, traces and vias in PCB layout, package interconnects, card connectors enables simulations to reveal the true problem of the design. We provide passive component models in various formats:

  • 2D/3D models

  • S parameter models

  • Spice models

  • Isolation parameters


 　

 IBIS Modeling
　

IBIS (I/O Buffer Information Specification) enables electronic designers to simulate system performance with actual IO buffers while protects IC designers’ intellectual property. We provide:

  • Accurate single-ended IBIS modeling services

  • Accurate differential IBIS modeling services

  • Application notes to help end-users enable IBIS models in various simulation environments

　

　

　

IC Package Design and Validation

　
　
　


　

As IO speed evolves from Mbps to Gbps or even higher in the near future, package interconnect parasitics can not be ignored any more. In some applications, packages have already become the bottle neck of IC performance. We provide fully customized solution to:

  • Flip Chip Packages

  • BGA (Ball Grid Array) Packages

  • CSP (Chip Scale Package) Packages

  • PGA (Pin Grid Array) Packages

  • MCM (Multi Chip Module) & SIP (System-in-Package)

  • QUAD Packages

  • Other Packages (QFP, SOP, PLCC, etc)